There has been a trend towards integrating previously off-chip circuits onto a single integrated circuit (IC), particularly in mobile devices. Such ICs are sometimes called system-on-chip (SoC) solutions and may include components such as high power metal-oxide semiconductor field-effect transistors (MOSFETs) used for driving circuits, buffers, amplifiers, or the like. The use of high power MOSFETs is limited to low driving currents, since power consumption on an IC is limited, particularly for mobile applications. However, higher driving currents are desired. Since power MOSFETs typically occupy more space on an IC than normal MOSFETs, space on the IC must also effectively be allocated.
FIG. 1 shows an example of a conventional complementary metal-oxide semiconductor (CMOS) layout 100 comprising an n-type metal-oxide semiconductor (NMOS) transistor 110 and a p-type metal-oxide semiconductor (PMOS) transistor 120. CMOS transistors are a particular type of MOSFET. An n-type MOSFET is one in which a conduction channel is formed by electrons and a p-type MOSFET is one in which a conduction channel is formed by holes. In FIG. 1, the NMOS 110 and PMOS 120 transistors share a common polysilicon gate 130 and lay on a common p-type substrate 140. The NMOS transistor 110 and PMOS transistor 120 may also have separate polysilicon gates, as desired. The NMOS transistor 110 is constructed by implanting two “n+” layers 150 for the drain and source in the p-type substrate 140.
The PMOS transistor 120 is constructed by implanting two “p+” layers 160 in an implanted n-well region 170. The n+ layer 150 represents a large number of free negative carriers, whereas the p+ layer 160 represents a larger number of free positive carriers available for conduction. The n-well 170 is created by an impurity implantation into the p-type substrate 140. A gate oxide layer 190 typically exists between the polysilicon gate 130 and p-type substrate 140 or n-well region 170. The NMOS transistor 110 and PMOS transistor 120 are separated by an insulting silicon dioxide (SiO2) layer 180.
In the CMOS layout 100, the current driving capability of the transistors is described by the relationship in Equation (1) as follows:
                                          I            ds                    ∝                      W            L                          ;                            Equation        ⁢                                  ⁢                  (          1          )                    where Ids is the current between the drain and source of the transistors 110 and 120, W is the width of the polysilicon gate 130 over the active area, and L is the length of the polysilicon gate 130 over the active area. Therefore, in order to provide higher driving currents for power applications, it is desirable to have a transistor with a higher W and lower L.
FIG. 2 shows an example of a conventional PMOS transistor circuit 200. Various resistors, which may be parasitic resistors, are created by the layers and the interconnection between layers of the PMOS transistor 200. In the source 201, Rspad 210 is the source pad resistance, Rslayer 220 is the resistance of layers connecting a pad to a source region, and Rds 230 is the drain to source MOSFET resistance. In the drain 202, Rdlayer 240 is the resistance of layers connecting a drain region to a pad, and Rdpad 250 is the drain pad resistance. RON 260 is the total resistance calculated by Equation (2) as follows:RON=Rspad+Rslayer+Rds+Rdpad+Rdlayer  Equation (2)An NMOS transistor, not shown, has similar resistance characteristics.
The power dissipated by the PMOS transistor 200 is calculated by Equation (3) as follows:P=RONIds2.  Equation (3)Similar to Equation (1), Ids is the current flow through the PMOS transistor 200 from the drain pad to the source pad. The source and drain pins in 200 are possible connection points to the pads, as desired. Therefore, the power dissipated is closely related to the total resistance RON 260. Since Ids of a power MOSFET is typically high, it is desired to reduce power dissipation by reducing RON 260. Of the resistances in Equation (2), Rds 230 may be reduced by taking into consideration the layout of the PMOS transistor 200.
FIG. 3 shows a layout of a conventional power MOSFET 300. The MOSFET 300 comprises drain and source pads 3101, 3102, . . . 310M, drain regions 320, source regions 330, a plurality of gates 340, and a plurality of VIAs 350. The pads 3101, 3102, . . . 310M may be used for signal input/outputs (I/O) or for supplying power to the MOSFET 300, as desired. A plurality of gates 340 is needed in order to provide higher driving currents, in accordance with Equation (1). A VIA is typically needed to interconnect different metal layers on the MOSFET 300. The Rds value of MOSFET 300 is related to the placement of the gates relative to the drain and source pads.
Conventional MOSFETs, such as MOSFET 300, are often inefficient due to the increasing distances between the drain pads and source pads relative to the active regions. Referring still to MOSFET 300 as an example, the distance between source pad 3101 to drain pad 310M relative to the active region 360 is greater than the distance between source pad 3103 and drain pad 3104 relative to the active region 362. The increased distance between source pad 3101 to drain pad 310M may result in poor biasing and driving currents of active region 360.
In view of the above, a need exists for reducing power dissipation in MOSFETs without the limitations of the prior art.